Position: R&D Engineer, IP Design/Verification
Location: IN01.
Job Description:
As part of the Solutions Group at Synopsys India, the selected candidate would be working on one or more aspects of the development of DesignWare family of synthesizable cores, including Specification, Architecting, Design, Verification and Release engineering for Synopsys IP products. The domains would span across areas such as AMBA(AHB,AXI), USB3, Gigabit Ethernet, Mobile storage, MIPI.
Post the orientation and training, the candidate would be assigned to work on either the design or verification tasks based on aptitude and business needs and will be part of a global team of expert Design/Verification Engineers
On the design side, the candidate would work on System level and RTL based hardware design coding languages such as Verilog, System Verilog, usage of tools for rule checking, Synthesis, timing closures and low power design concepts such as unified power flows.
On the verification side, candidate would work on latest verification methodologies such as UVM, VMM. The verification tasks would include building CRV based complex test environment, test case writing in OOPS based languages such as SystemVerilog, Vera, running tests and debugging failures, Functional coverage implementation and would involve usage of industry standard simulators such as VCS.
It is essential that the individual has the aptitude to work in the VLSI domain, has good communication skills and is able to demonstrate good analysis, debug and problem solving skills and be self-driven.
Qualification requirements:
BTech or MTech in Electrical/Electronics Engineering or allied subjects with minimum qualification marksof 70 % or CGPA of 7.0 and above, in aggregate of all semesters.
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